Memory chips: DRAM, NAND and HBM

A processor does arithmetic. It cannot do anything useful without numbers to work on, and those numbers have to be stored somewhere close enough to fetch quickly. That storage is memory. The word covers a family of very different chips that all answer the same question: how fast, how big and how cheap can a place to keep bits be? The honest answer is that you can pick two. Fast memory is small and expensive. Large memory is slow and cheap. Every computer, from a phone to an AI data center, is built as a stack of layers that trade these properties against each other.

Engineers call this stack the memory hierarchy. The top layers sit next to or inside the processor and are tiny and extremely fast. The bottom layers are huge and slow and keep data when the power is off. In between sits the layer most people mean when they say 'RAM'. This piece follows the hierarchy from the top down, because the story of AI and memory is a story about which layer has become the scarce one.

SRAM (static random-access memory) stores each bit in a small circuit of about six transistors that holds its state as long as power is on. It is built on the same manufacturing process as the processor logic, so it sits right next to the compute cores. It is the fastest memory available, with access times of roughly a nanosecond (a billionth of a second) in typical designs. The cost is area: six transistors per bit is a lot of silicon, so on-chip SRAM is measured in megabytes, not gigabytes. CPU caches and the small on-chip buffers of AI accelerators are SRAM. It does not scale well with newer manufacturing nodes, which is one reason designers cannot simply add more of it.

DRAM (dynamic random-access memory) stores each bit as a charge in a tiny capacitor, switched by a single transistor. One transistor and one capacitor per bit is far denser and cheaper than SRAM. The catch is in the name: the charge leaks away in milliseconds, so the chip must continually read and rewrite every cell (a 'refresh'). DRAM is volatile, meaning it forgets everything when power is lost. Access time is typically tens of nanoseconds, around fifty to a hundred times slower than SRAM, but capacity is measured in gigabytes. This is the memory in a laptop (DDR), a phone (LPDDR) and a server (DDR5 modules, often 64 to 256 GB each).

DRAM is made by only a handful of companies on some of the most advanced manufacturing lines in the world. The process generations are named with a letter and a number (1a, 1b, 1c) that stand for successive shrinks of the 10-nanometer-class cell. Making the capacitor smaller while keeping enough charge is hard physics, and each shrink now delivers less benefit than it used to. That matters later, when we look at why supply of bits cannot simply be switched on.

HBM (high-bandwidth memory) is still DRAM, but stacked: several DRAM dies are placed on top of each other and joined by thousands of vertical copper connections called through-silicon vias (TSVs). The stack sits right beside the processor on a shared base, instead of far away on a separate module. Because the connection is so wide (1,024 bits per stack through HBM3E, 2,048 bits in HBM4), it moves enormous amounts of data per second at lower energy per bit. Chapter 3 covers it in detail. For now, think of HBM as the premium, short-distance, very-wide version of DRAM, and it is the layer AI accelerators depend on.

NAND flash keeps bits as trapped electric charge in cells that persist without power. It is the chip inside every phone, SSD (solid-state drive) and USB stick. Modern NAND is built in 3D: instead of shrinking cells on a flat plane, makers stack hundreds of layers of cells vertically and punch channels through them. Flash is far cheaper per bit than DRAM, but much slower: reads take tens of microseconds, roughly a thousand times longer than DRAM, and writes wear the cells out over time. Data-center SSDs are the layer that holds datasets, model checkpoints and, increasingly, the files AI systems read from.

At the bottom of the pyramid are spinning hard disk drives (HDDs), made by Seagate, Western Digital and Toshiba, and magnetic tape. They are slow, with millisecond access, but they remain the cheapest way to hold very large volumes of data, which is why cloud providers still use them for bulk and archival storage. They are not memory chips, but they are the outer ring of the same trade-off and are part of the map in the final chapter.

The figures in the table are order-of-magnitude typical values used in textbooks and vendor materials, not measurements of any one product. The important point is the ratio between layers: each step down is roughly ten to a thousand times slower and ten to a hundred times cheaper per bit.

Latency is how long you wait for the first bit to arrive. Bandwidth is how many bits per second can flow once the data is moving. A tanker truck has terrible latency and enormous bandwidth; a courier on a motorbike is the reverse. Most everyday computing is limited by latency, which is why caches exist. AI is different. Its workloads move gigantic blocks of numbers in predictable patterns, so what limits them is bandwidth: how fast the pipe from memory to the compute cores can pour. Almost everything in this piece follows from that single fact.

DRAM and NAND were for decades the textbook commodity: standardized parts, interchangeable between suppliers, priced day to day in spot and contract markets. HBM changes that. It is customized to a specific accelerator, qualified by the customer over many months, and sold under negotiated annual contracts. As chapter 5 and 6 show, that split between commodity bits and specialized bits is central to why the industry looks different in 2026 than it did in any earlier cycle.

In 1995 the computer scientists William Wulf and Sally McKee published a short paper titled 'Hitting the Memory Wall'. Their argument was simple. Processor speed had been improving by tens of percent each year, memory speed by far less, so eventually the time spent waiting for data would dominate everything else. Three decades later the argument has become the central constraint of AI hardware. A modern accelerator can perform enormous numbers of operations per second, but it can only do so if the numbers arrive on time. When they do not, expensive compute sits idle.

Engineers describe this with a ratio called arithmetic intensity: how many calculations are done per byte fetched from memory. If a workload does many calculations on each byte, the processor is the limit ('compute-bound'). If it does few, memory is the limit ('memory-bound'). Training a large model in big batches is relatively compute-heavy. Serving a model to users, one token at a time, is not.

A large language model produces its answer one token (roughly a word fragment) at a time. To produce each token, the hardware must read essentially all of the model's weights from memory, do a modest amount of arithmetic with them, and then do it again for the next token. The weights are the learned numbers that make up the model. A model with 70 billion parameters stored at 8 bits each occupies about 70 gigabytes. Every generated token needs those 70 gigabytes streamed past the compute cores.

This gives a simple upper bound. If the memory system can deliver 3.35 terabytes per second (the published HBM3 bandwidth of Nvidia's H100 SXM accelerator), then one stream of a 70 GB model cannot produce more than roughly 48 tokens per second, no matter how many arithmetic units the chip has. That is an illustrative calculation from public specifications, not a benchmark, and in practice servers batch many users together to share each read of the weights. But the lesson stands: the speed of text generation is set far more by memory bandwidth than by raw compute.

Bandwidth is about speed. Capacity is about whether the model fits at all. Weights must be held in fast memory, not fetched from a disk each time. Frontier models have hundreds of billions to trillions of parameters. Even at reduced numerical precision, they occupy hundreds of gigabytes to terabytes, more than the HBM on one accelerator. The usual solution is to split the model across many accelerators and link them with fast networking. That means that part of the reason for buying more accelerators is simply to buy more memory capacity, and the amount of HBM per accelerator has risen with each generation.

There is a third consumer of memory that grows as models are used more heavily. To avoid recomputing everything for every new token, a transformer model saves intermediate results for each token it has already processed. These saved results are called the key-value cache, or KV cache. It grows linearly with the length of the conversation or document and with the number of users being served at once.

An illustrative calculation shows the scale. For a model shaped like a 70-billion-parameter open model (80 layers, 8 key-value heads, 128 values per head, 16-bit numbers), the cache costs about 2 x 80 x 8 x 128 x 2 bytes, or roughly 0.33 megabytes per token. A single conversation with 128,000 tokens of context therefore needs about 42 gigabytes of cache, on top of the weights. A server handling dozens of such conversations needs terabytes. Real systems use compression, sharing and smarter attention schemes to cut this, but the direction of travel is clear: longer context windows, AI agents that keep long histories and multi-step reasoning all increase the cache.

Training a model is a one-time, very large job. Serving it to millions of users is a continuing cost that scales with usage. As AI products become widely used, and as 'reasoning' models generate long chains of intermediate tokens before answering, the share of AI compute spent on inference grows. Inference is the memory-bound part. This is why memory suppliers, rather than only chip designers, have been described as the gating factor for AI capacity in company commentary through 2026.

Accelerator makers responded by attaching more and faster memory to each chip. The pattern across public specifications is consistent: each generation of accelerator carries more HBM stacks, each stack is taller and faster, and memory becomes a larger share of the bill of materials. Nvidia's H100 shipped with 80 GB of HBM3 at 3.35 TB/s. Later parts moved to HBM3E with substantially higher capacity and bandwidth, and the next platform, called Vera Rubin, is reported to use HBM4 (Samsung and SK hynix reporting, October 2026).

Bandwidth per stack has risen by a factor of 16 in a decade. Yet accelerators now carry six to eight stacks each, and the total demand from AI data centers has grown faster still.

The obvious fix, attaching more ordinary DRAM modules, does not work well because of physics. Conventional DRAM connects to the processor through a narrow channel on a circuit board, with signals traveling centimeters. Pushing more data through that channel needs more pins, more power and faster signaling, all of which hit limits. HBM sidesteps this by moving the memory a few millimeters from the compute die and widening the connection to thousands of wires. That solution is brilliant but hard to build, which is why the bottleneck moved from the chip designers to the factories that can stack and package memory.

Moving a bit from memory to the processor costs far more energy than doing arithmetic on it. Public discussions by chip designers have long cited data movement as the dominant energy cost in AI systems, and shorter, wider paths such as HBM reduce energy per bit moved. As data centers become constrained by electricity supply, energy per bit moved becomes an economic as well as an engineering metric. This is one reason new architectures (chapter 7) focus on moving compute closer to the data.

An HBM stack starts as ordinary DRAM wafers. Each wafer is thinned to a fraction of the thickness of a human hair, cut into dies, and drilled with thousands of tiny vertical holes that are filled with copper. These are the through-silicon vias (TSVs). The dies are then stacked (4, 8, 12 or 16 high), with microscopic solder bumps between layers aligning each via with the one above. A base die at the bottom contains the interface logic and connects the stack to the processor. In the packaging step, the stacks and the accelerator die are mounted side by side on a silicon interposer, a thin slab of silicon wiring that links them with thousands of short connections. This arrangement is often called 2.5D packaging.

Every step is difficult. Thinned dies are fragile. Bonding twelve or sixteen layers means a single bad die can scrap the whole stack. Heat from the lower layers has to travel up through the stack. Suppliers use different bonding and filling methods: SK hynix has publicly described its mass reflow molded underfill process (MR-MUF), while Samsung has used thermal compression with a non-conductive film. Equipment for precise thermocompression bonding comes from a small group of toolmakers, including Hanmi Semiconductor, which has reportedly supplied SK hynix.

Yield means the fraction of manufactured units that work. In a 12-high stack, the yield of the stack is roughly the product of the yields of every step and every die, so small losses at each stage compound. This is why HBM costs far more per bit to make than standard DRAM, and why a new generation can take quarters to ramp. It also explains why supply cannot be added quickly: capacity requires not only DRAM wafers but also TSV etching, stacking, bonding, testing and advanced packaging lines.

JEDEC, the industry standards body, defined the first HBM standard in October 2013 and updated it with HBM2 in January 2016. HBM3 was announced on January 27, 2022, with a pin speed of 6.4 Gb/s and bandwidth of 819 GB/s per stack. HBM3E, an enhanced version sold by the vendors, runs at roughly 9.2 to 9.8 Gb/s for about 1.2 TB/s per stack (Micron, SK hynix and Samsung figures), with up to 12 or 16 layers, giving 36 to 48 GB (SK hynix). The HBM4 standard (JESD270-4) was published on April 16, 2025: it doubles the interface width to 2,048 bits and allows up to 2 TB/s per stack and up to 64 GB with 16 layers (JEDEC press release, April 16, 2025). In July 2026 JEDEC published a variant called SPHBM4 (JESD330-4) that uses a narrower 512-bit external interface on standard organic substrates, avoiding the silicon interposer.

1. Oct 2013JEDEC publishes the first HBM standard (JESD235): 128 GB/s per stack. SK hynix's first-generation parts are 4-high stacks of 1 GB.
2. Jan 2016HBM2 doubles bandwidth to 256 GB/s per stack.
3. Jan 2022HBM3 announced: 819 GB/s per stack.
4. Apr 2025HBM4 final standard: 2,048-bit interface, up to 2 TB/s and 64 GB per stack.
5. May 2026Samsung reportedly delivers 12-layer HBM4E samples.
6. Jul 2026JEDEC publishes SPHBM4 (JESD330-4), a 512-bit variant for organic substrates.
7. Q4 2026SK hynix says HBM4 should pass HBM3E in shipment volume and revenue and become its main HBM product.

Nvidia is the largest buyer of HBM, and each memory supplier must qualify its stacks on each Nvidia platform before volume orders: a process of samples, reliability tests and system-level validation that can take many months. SK hynix has been the first and largest supplier of HBM3 and HBM3E to Nvidia. Micron began volume HBM3E shipments in 2024. Samsung was slower to qualify on HBM3E but has reportedly moved ahead in HBM4.

As of October 2026, press reports state that Samsung is supplying HBM4 for Nvidia's Vera Rubin platform and that AMD is adopting HBM4 for its Instinct MI455X accelerator. Reports also say SK hynix committed most of its 2026 HBM4 output to Nvidia. Samsung has reportedly passed Nvidia's verification for 12-layer HBM4E, though Samsung has not publicly confirmed that. Counterpoint Research is quoted as expecting Rubin to keep 12-layer HBM4 stacks. These items come from secondary outlets and should be treated as reported rather than confirmed by Nvidia.

On who leads HBM in 2026, the sources diverge. TrendForce's 2Q26 DRAM report (September 2026) says SK hynix had the highest HBM share of bit shipments among the big three, and that Samsung had the strongest bit shipment growth thanks to early HBM4 mass production. One outlet estimates that Samsung's HBM revenue of about $8.7 billion overtook SK hynix's roughly $7.6 billion in the third quarter of 2026. That is an estimate from a secondary source, not a company-reported figure, and it conflicts in emphasis with TrendForce. A reader should treat the HBM ranking as contested until the companies disclose figures.

SK hynix said on October 28, 2026, with its third-quarter results, that its HBM and other DRAM products are sold out through 2029, that long-term agreements already cover more than half of its production capacity for 2027 and 2028, and that it expects supply to keep falling short of demand through 2030 (Korea Times, October 28, 2026). It also said its M15X fab would reach full capacity by the end of 2026 to raise HBM4 output. Micron's reporting is consistent in direction: one analysis of its September 2026 results says the vast majority of 2027 HBM supply is already contracted at significantly higher prices. Micron's own press release for fiscal Q4 2026 refers to 'Strategic Customer Agreements' that add confidence in the durability of its performance, though it gives no HBM figures.

Public disclosure of HBM prices is thin. Suppliers negotiate annually with a few buyers and do not publish price lists. What is available are indirect signals. TrendForce said in November 2025 that it forecast total DRAM contract prices, including HBM, to rise 50 to 55 percent quarter on quarter in 4Q25. A class-action lawsuit filed against Samsung, SK hynix and Micron in June 2026 alleges coordinated production shifts from DDR3 and DDR4 to HBM, and states that prices rose reportedly 700 percent over four years; those are allegations in a complaint, not findings. The companies' response to the complaint was not located in this research. This piece does not give a price per gigabyte for HBM because no primary, dated source for one was found.

HBM consumes much more wafer capacity per bit than standard DRAM. Micron has said that HBM3E uses roughly three times the wafer supply of DDR5 for the same number of bits. The reason is a mixture of larger die sizes, the extra base die and stack yield losses. Because the three suppliers share the same wafer starts, every wafer devoted to HBM is a wafer not producing DDR5 for PCs and servers, or LPDDR for phones. This is the mechanism that links the AI boom to shortages in consumer electronics, covered in chapter 6.

Memory consolidated over decades. Dozens of DRAM makers existed in the 1980s and 1990s; after a string of bankruptcies in the 2008 to 2012 period (including the German firm Qimonda and the Japanese firm Elpida, whose assets Micron acquired in 2013), three companies were left with the scale to compete at the frontier: Samsung, SK hynix and Micron. Together they accounted for about 85 percent of DRAM revenue in 2Q26, per TrendForce, with China's CXMT fourth at 9.5 percent.

The chart shows a change of leadership. In 3Q25 SK hynix was first with 33.2 percent, narrowly ahead of Samsung at 32.6 percent. By 2Q26 Samsung had 39.4 percent and SK hynix 24.9 percent. TrendForce attributes this to the mix: SK hynix has the highest share of HBM in its shipments among the three, which holds down its average selling price per bit, while conventional DRAM contract prices rose faster than HBM prices in 2026 and Samsung had the largest exposure to conventional bits. Market share by revenue therefore reflects pricing as much as volume.

NAND flash has more players because its history differs. Toshiba invented flash; its memory unit was sold in 2018 to a consortium led by Bain Capital and became Kioxia, which listed in Tokyo in December 2024. SanDisk, Kioxia's joint venture partner in Japanese fabs, was spun out of Western Digital in February 2025. Micron and Samsung are the long-time competitors, and SK hynix entered large-scale NAND by acquiring Intel's NAND business, now Solidigm. China's YMTC is the newest entrant.

TrendForce reports that the top five NAND brands had combined revenue of about $68.87 billion in 2Q26, up 77 percent from 1Q26, with Micron's revenue up 99.2 percent to $11.85 billion and rising to third place. The published share columns in the secondary report do not reconcile with each other, so this piece gives revenue and not shares for NAND. For 1Q26, TrendForce data cited by a Taiwanese outlet put Samsung at about $13.51 billion and the SK group near $7.53 billion. TrendForce expected strong AI-driven demand for enterprise SSDs to continue in 3Q26 while smartphone and PC demand stays weak, and said suppliers are prioritizing capital spending on DRAM and HBM, which limits new NAND capacity.

China has funded memory as a national priority. ChangXin Memory Technologies (CXMT) makes DRAM and, per TrendForce, ranked fourth with $14.62 billion in 2Q26 revenue, up 99.3 percent from the prior quarter, the fastest growth among the top four. It completed an IPO on Shanghai's STAR Market on July 27, 2026; reports describe it as the biggest STAR Market IPO, raising about 66.6 billion yuan (about $8.6 billion in one report), with shares jumping several-fold on the first day. Capacity estimates vary: SemiAnalysis projects it could reach 500,000 wafers per month by the end of 2028, while Morningstar Asia estimates 325,000 wafer starts per month by the end of 2026.

Yangtze Memory Technologies (YMTC) makes NAND. Its parent filed for a Shanghai IPO in August 2026 seeking about 33 billion yuan (around $4.9 billion), though another report gives 29.5 billion yuan. Jefferies estimated YMTC's share of global NAND at 13 percent in 1Q26, and one report says it is building three new factories that would more than double capacity by the end of 2027. These are estimates and press reports; the company's prospectus is the primary source.

The United States introduced export controls in October 2022 that restricted China's access to equipment for advanced NAND and DRAM manufacturing, and added YMTC to its Entity List in December 2022. In December 2024 it also restricted exports of HBM to China. Control of tools from ASML, Applied Materials, Lam Research and Tokyo Electron limits how fast Chinese makers can move to the most advanced nodes. CXMT is reported to lag in HBM largely because it cannot get the most advanced tools. Reports in 2026 say YMTC is testing domestic etch, deposition and test equipment.

Politics remain unsettled. One secondary source says a brief Federal Register posting in February 2026 removed CXMT and YMTC from the Entity List; this research could not confirm that from a primary source and it is reported here as unverified. Other items are better documented in secondary press: US senators introduced the MATCH Act in April 2026 naming CXMT, YMTC and others for tougher equipment and servicing limits, and the Defense Department's updated Section 1260H list in June 2026 again identified CXMT as a Chinese military company. Readers should check the Federal Register and the Department of Defense for current status.

HBM ships inside the accelerators Nvidia sells, so where those accelerators end up matters here too: Culper Research, a short seller that posted on 13 May 2026 that it is short Nvidia, says over 20% of Nvidia's FY2026 compute revenue stayed driven by China through Southeast Asian intermediaries (Culper Research, 13 May 2026, report not opened; Benzinga, May 2026). Nvidia has said diversion claims about one customer were investigated and debunked, and I found no reply to Culper by name (The Hill, 29 Oct 2026). The Nvidia page (/investing/nvidia) sets out both sides.

Geography matters because memory fabs are huge and slow to build. South Korea hosts Samsung and SK hynix's flagship fabs (SK hynix's M15X and the planned Yongin cluster; Samsung's Pyeongtaek complex). Japan hosts Kioxia and SanDisk's joint-venture fabs and Micron's Hiroshima DRAM fab. Taiwan hosts Micron and the smaller DRAM makers Nanya, Winbond and PSMC. The US has a small share of capacity today. Under the CHIPS and Science Act, Micron was awarded up to roughly $6 billion in grants (finalized December 2024, with later increases reported) for fabs in Idaho and New York, and SK hynix was awarded up to $458 million for a HBM packaging plant in Indiana. Those awards and timetables should be checked against current Department of Commerce documents; the figures here are from 2024 announcements.

The Korean companies also run large fabs in China (Samsung's NAND in Xi'an; SK hynix's DRAM in Wuxi and NAND in Dalian), which have operated under US licensing arrangements. In 2025 the US moved to revoke the special status that eased equipment shipments to them; this research did not retrieve the current status, so it is flagged as a gap.

Memory has been through price-fixing cases before. The US Department of Justice charged DRAM makers with fixing prices from 1999 to June 2002; Infineon agreed to pay a $160 million fine (announced September 2004), Hynix $185 million (April 2005) and Samsung $300 million (October 2005), and the European Commission fined nine makers a total of about 331 million euros in May 2010. A 2018 class action alleging 2016 to 2017 price fixing was dismissed, and the dismissal was affirmed in March 2022. A new class action filed on June 25, 2026 (Garciaguirre v. Samsung Electronics) makes allegations about HBM-related production shifts. An allegation is not a finding, and consolidation to three producers will keep attracting regulatory attention whenever prices spike.

Memory is a commodity business with very long lead times. A new fab takes two to three years to build and costs tens of billions of dollars, so suppliers decide on capacity before they know what demand will be. When prices are high, everyone adds capacity; when that capacity arrives together, prices crash below cash cost; then capital spending is cut and the cycle turns. The pattern has repeated since the 1980s, and the industry's leading firms have swung between large profits and large losses.

1. 1999-2002Period of the DRAM price-fixing conspiracy later prosecuted by the US Department of Justice.
2. 2008-2012Industry downturn; Qimonda (2009) and Elpida (2012) go bankrupt, leaving three major DRAM makers.
3. Jun 2016 to Jan 2018DRAM prices nearly tripled in the supercycle driven by smartphones and servers.
4. 2019Prices fall and inventories rise after the 2018 peak.
5. 2022-2023Post-pandemic glut: Micron reports a net loss in fiscal 2023, SK hynix an operating loss for 2023, and the big three cut output and capital spending.
6. 2023-2024Recovery led by HBM and data-center demand.
7. 2025-2026AI-driven shortage across DRAM and NAND, with record prices and profits.

The scale of the last downturn is visible in Micron's annual revenue. It was about $30.8 billion in fiscal 2022, fell to about $15.5 billion in fiscal 2023, with a large net loss, then rose to about $25.1 billion in fiscal 2024 and $37.38 billion in fiscal 2025. The fiscal 2026 figure of $133.19 billion (year ended September 3, 2026) is more than three and a half times fiscal 2025 and more than eight times the 2023 trough.

The earlier years in the chart are rounded from Micron's annual filings; the FY2025 and FY2026 values are from the October 2026 press release filed with the SEC.

TrendForce data show how fast it went. DRAM industry revenue was $41.4 billion in 3Q25, up 30.9 percent from the prior quarter. By 1Q26 it was about $97.0 billion, and in 2Q26 it was $154.73 billion, up 59.5 percent in the quarter. That is 3.7 times the 3Q25 level in three quarters. TrendForce says supply expansion continues to lag demand growth, with supplier inventories at historic lows.

Contract prices explain most of it. TrendForce revised its 1Q26 forecast for conventional DRAM contract prices in February 2026 to a 90 to 95 percent increase quarter on quarter, up from an earlier forecast of 55 to 60 percent, as reported by a secondary source; that would be the largest quarterly rise in the data series cited. For 3Q26, TrendForce expected conventional DRAM contract prices to rise 13 to 18 percent. A separate analyst estimate cited in press put SK hynix's average selling prices up about 22 percent for DRAM and 15 percent for NAND in 3Q26 (an estimate, not a company figure).

Micron's fiscal Q4 2026 (quarter ended September 3, 2026, reported in autumn 2026) had revenue of $54.23 billion, compared with $41.46 billion in the prior quarter and $11.32 billion a year earlier. GAAP gross margin was 86.8 percent, or $47.05 billion of gross profit. It generated $43.97 billion of operating cash flow in the quarter. For fiscal Q1 2027 it guided to revenue of $61.5 billion plus or minus $1.5 billion and a gross margin of about 86 percent.

SK hynix reported on October 28, 2026 revenue of 104.6 trillion won for July to September, up 328 percent on the year and its first quarter above 100 trillion won, with operating profit of 83.33 trillion won, up 632 percent, and an operating margin near 80 percent. Samsung Electronics pre-announced a record third-quarter operating profit of about 107.4 trillion won, up around 783 percent, for the whole company (operating margin near 55 percent), attributed to HBM4 and memory price gains. Samsung's memory-specific figures were not confirmed in the sources retrieved.

There are three arguments that this cycle differs. First, a large share of demand comes from a small number of buyers with long-term plans (hyperscalers and AI labs), and suppliers now sign multi-year agreements: SK hynix says long-term deals cover more than half of 2027 and 2028 capacity, and Micron cites Strategic Customer Agreements. Second, HBM absorbs a high share of wafers, which removes supply from commodity markets. Third, suppliers have been prioritizing DRAM and HBM investment over NAND, and capital intensity is rising with each node. Against these points, the structural feature that has driven every previous bust remains: capacity decisions made at high prices arrive years later. ASML's CEO said in October 2026 that some customers were interested in placing orders for 2029 and even 2030, a sign that capacity plans are being made far ahead.

Another sign of rising supply response: Micron said with its fiscal Q4 2026 results that it would raise fiscal 2027 capital spending, guiding to about $11.5 billion in the first quarter and about $25 billion in the first half, with most of the increase for construction to speed cleanroom availability in late calendar 2028 and beyond. Past cycles show that capacity added at the top arrives at the bottom.

Industry watchers use a small set of indicators. Contract price (what large buyers pay under quarterly or monthly deals) lags spot price (the market for loose chips), so spot softening is an early warning. Supplier and customer inventory, usually measured in weeks of sales, signals pressure: TrendForce notes supplier inventories are at historic lows in 2026. Capital spending and wafer-capacity announcements show future supply. Finally, device sell-through (smartphones, PCs) tells whether consumer demand is giving way, which is happening in 2026 as chapter 6 describes.

In a commodity business with a nearly fixed cost base, price changes drop straight to profit. That is why memory margins swing from negative to extraordinary. Micron's GAAP gross margin was negative in fiscal 2023, the last trough. For all of fiscal 2026 it was 80.7 percent ($107.5 billion of gross profit on $133.19 billion of revenue), and 86.8 percent in the September 2026 quarter. SK hynix reported an operating margin of about 80 percent for the third quarter of 2026, compared with roughly 47 percent in the same quarter of 2025, which is derived from the reported year-on-year changes. Samsung reported a company-wide operating margin near 55 percent in its preliminary third-quarter figures.

These margins are far above those of the logic chip designers and foundries that dominate headlines, and they are the result of price rises on a nearly fixed cost base. For context, SK hynix's operating margin one year earlier was less than 50 percent.

Memory is one of the most capital-intensive industries. A leading-edge DRAM fab costs many billions of dollars, and each node shrink requires new equipment, notably extreme ultraviolet (EUV) lithography tools from ASML, which are used for a growing number of layers in advanced DRAM. Micron's net capital spending was $27.37 billion in fiscal 2026 and $10.77 billion in the last quarter, and it guided to roughly $25 billion in the first half of fiscal 2027. ASML said in October 2026 that it expects memory net system sales to grow around 75 percent in 2026, citing customer capacity expansion and wider EUV adoption on advanced DRAM nodes, and that memory made up about 49 percent of its second-quarter system sales.

Capital spending per bit of capacity is not publicly disclosed in a comparable form and this research did not find a reliable source for it. What is known is the direction: each DRAM node yields fewer extra bits per wafer than the last, and HBM and 3D NAND add process steps. The result is that adding a bit costs more than it did, which supports a higher long-run price floor, but also means suppliers who build aggressively commit large fixed costs.

Every DRAM maker decides how to split wafer starts between three product families: HBM for AI accelerators, server DRAM, and mobile and PC DRAM. HBM earns the highest price per bit and carries long-term contracts but uses roughly three times the wafer per bit of DDR5, according to Micron. Server DRAM for AI servers is next. Consumer DRAM for phones and PCs earns the least. When the choices are made at the margin, consumer products lose supply, which pushes their prices up and raises costs for device makers who cannot easily pass them on.

TrendForce reported in May 2026 that surging mobile DRAM contract prices in 2Q26 put heavy cost pressure on smartphone brands, and a later press report said Samsung was seeking another LPDDR price increase of more than 20 percent for 3Q26 (a single-outlet report). For PCs, IDC cut its 2026 forecast to a 4.9 percent decline in unit shipments from an earlier 2.4 percent decline and projected PC average selling prices 4 to 8 percent higher depending on conditions. One article citing TrendForce puts the 2026 smartphone market decline at 13 percent. These forecasts have shifted over the year, so the direction, not the exact figure, is the lesson: memory cost is being passed through to consumers, and unit demand is falling.

Memory is typically a small slice of a device's cost in normal years, but when prices more than double, it becomes material. Device makers respond by raising prices, cutting memory configurations, shifting to older memory types or locking in supply with long contracts. This is also why smaller DRAM makers focused on older products (DDR3, DDR4) such as Nanya and Winbond grew revenue 68 and 76 percent in 2Q26: demand shifted to them as the majors moved capacity to newer products.

In 2026 two shortages coexist. AI demand pulls every high-end bit. Consumer products face cost inflation and reduced supply. The same event looks like a boom for suppliers and a tax for device buyers. Suppliers say they cannot increase output quickly: TrendForce notes that new capacity went mostly to server use and bit shipments grew only modestly, and that smaller suppliers gain share by absorbing demand the majors cannot serve during process migrations.

High profits flow to balance sheets and shareholders. SK hynix announced a shareholder return plan of 100 trillion won for the year (at least 30 trillion won in dividends and more than 60 trillion won in buybacks), approved a third-quarter dividend of 14 trillion won (20,000 won per share) and a new 20 trillion won buyback, per the Korea Times on October 28, 2026. Micron ended fiscal 2026 with $73.48 billion in cash, marketable investments and restricted cash. The balance between returning cash and funding fabs is one of the main questions for the next phase of the cycle.

If the bottleneck is bandwidth and capacity next to the processor, three directions are open: add a new tier of memory, make the existing tier larger and cheaper, or reduce the amount of data that has to move. Each has an active research or product path, and each has different timing. None has been shown to remove the dependence on HBM in the short term.

Compute Express Link (CXL) is an open standard, introduced in 2019, that lets processors share memory over the same physical connections used by PCI Express. It allows servers to attach extra memory modules beyond what fits on the motherboard's standard slots and, in later versions, to pool memory across several machines so that unused capacity in one server can be used by another. For AI, CXL can add a large, slower tier of DRAM behind HBM, for instance for the KV cache. Samsung, SK hynix and Micron have all announced CXL memory expansion products. This research did not retrieve a dated figure for CXL revenue or adoption in 2026, so its scale should be treated as unquantified and likely small relative to HBM.

High-bandwidth flash is the most concrete new idea of 2026. The concept is to stack many NAND dies with vertical connections, like HBM, and place the package next to the accelerator, giving far more capacity than DRAM at lower cost per bit. SanDisk and SK hynix published the first HBF specification through the Open Compute Project at the time of the FMS 2026 conference. It covers packages of up to 512 GB built from 8-high or 16-high NAND stacks, in three bandwidth grades from roughly 0.4 to 3.0 TB/s, linked to processors via the UCIe chiplet interface. One report says samples of the first AI inference devices using HBF are expected in early 2027.

The limits are inherent in flash: write endurance is finite and write latency is higher than DRAM, so early uses are expected to be read-heavy, such as holding model weights and long-lived cache for inference. Kioxia is reported to be developing its own high-bandwidth flash with up to 32 stacked dies, with Nvidia reportedly involved in partner discussions. The expected selling point is cost: flash is cheaper than DRAM, so HBF could, in the words of a March 2026 report, undercut HBM for inference and edge servers. All of this is pre-production; no commercial HBF volumes had been reported as of November 3, 2026.

Processing in memory places simple arithmetic units inside or beside the memory chip, so that data is processed where it sits instead of being shipped to the processor. Samsung demonstrated HBM-PIM in 2021 and SK hynix has described an accelerator-in-memory product. The approach suits operations that read huge amounts of data and do little with it, which describes the attention step in inference. The barriers are software support, the cost of adding logic to a DRAM process that is optimised for capacitors, and the fact that GPUs already have a sizeable ecosystem. In this research, no large-volume PIM deployment was found in 2026 sources.

HBM stacks finished chips. 3D DRAM would instead build the memory cells themselves in layers within a single die, as 3D NAND did for flash. The motive is that conventional DRAM scaling is slowing: it gets harder to shrink the capacitor. Memory makers and research groups have published concepts and prototypes for vertical-channel and stacked-cell designs, but no source retrieved here shows a product in volume production. It is a long-horizon item, relevant to the 2030s.

• Oversupply. Every previous peak ended with a glut. Micron is raising capital spending (about $25 billion in the first half of fiscal 2027), SK hynix is bringing M15X to full capacity by end of 2026 and building a cluster at Yongin, CXMT is estimated to reach 325,000 to 500,000 wafers per month by end-2026 to 2028, and YMTC may double capacity by end-2027 (estimates from Morningstar Asia, SemiAnalysis and press). If AI demand slows as capacity lands, prices could fall quickly.
• Customer concentration. A small group of AI buyers drives a large share of incremental demand. If their capital spending is cut, or if they push back on price, suppliers have limited alternatives. Long-term agreements protect volumes only to the extent that customers honour them or terms are enforceable.
• HBM could become a commodity. Once three suppliers qualify at Nvidia and AMD, price competition can increase. HBM4E, HBM5 and SPHBM4 are designed to make the product more standard, which could reduce supplier pricing power.
• Efficiency. Models can be compressed, quantised and served with less memory per token; new attention methods reduce KV cache size. If the memory per unit of AI output falls faster than usage grows, demand per dollar of AI capex shrinks.
• New tiers. HBF, CXL and PIM could shift some demand from HBM to cheaper memory, though they could also create new demand for NAND and DRAM.
• Demand destruction in consumer devices. PC and smartphone volumes are forecast to fall in 2026 (IDC: PCs down 4.9 percent), and a prolonged price spike can lead consumers and makers to delay purchases, reducing the base demand that the cycle depends on.
• Policy and legal risk. Antitrust litigation filed in June 2026 alleges coordinated production shifts, export controls can change market access, and Chinese suppliers are expanding with state-backed finance and public listings in 2026.

Equity markets have shown how contested the outlook is. SK hynix's share price fell 18.8 percent from 1,693,000 won on September 1, 2026 to 1,374,000 won on October 27, then rose 10.89 percent on October 28 after its results (Korea Times). On October 24, the shares rose 3.3 percent when a planned IPO of its Solidigm unit was scrapped. Micron's shares fell after hours following its September report, with reports attributing it to its higher capital spending plan despite beating estimates and guiding above expectations (Stocktwits report of the day). These moves show investors weighing record profits against the capacity response.

• Contract price growth slowing, then turning negative, in the TrendForce monthly and quarterly series.
• Spot prices falling below contract prices for several months.
• Supplier inventory rising from historic lows.
• Hyperscaler capital spending guidance for 2027.
• Suppliers' capital spending and wafer capacity announcements, especially CXMT and YMTC.
• HBM4 qualification news at Nvidia and AMD, and the first reported HBF sampling in early 2027.

This chapter lists listed companies and describes their exposure to memory, using the dated facts gathered in this piece. It is a map of who does what, not a view on any security. Listing codes are given for orientation and should be verified with an exchange before use.

Western Digital and Seagate are not memory-chip makers, but they sit on the lowest rung of the hierarchy and compete with flash for capacity workloads. Their exposure is to the volume of data stored, not to DRAM or NAND prices directly, though higher SSD prices can influence storage mix decisions.

Equipment makers are exposed to capital spending, not to chip prices directly. They tend to benefit when suppliers raise capital budgets and suffer when those are cut, with a lag. Micron's guide for about $25 billion of capital spending in the first half of fiscal 2027 and ASML's remark about orders for 2029 and 2030 are the dated markers for 2026.

• CXMT (Shanghai STAR Market): listed July 27, 2026; DRAM revenue $14.62 billion in 2Q26 and 9.5 percent share (TrendForce).
• YMTC parent: filed for a Shanghai IPO in August 2026 seeking about 33 billion yuan, per Caixin Global; one report gives a smaller amount. Not yet trading as of the sources retrieved.
• Nanya Technology and Winbond (Taiwan): older-generation DRAM, 2Q26 revenue $2.61 billion and $1.00 billion respectively, up 68.3 percent and 75.8 percent on the quarter (TrendForce).
• Accelerator buyers such as Nvidia and AMD are the principal customers for HBM, and device makers (phones, PCs) are the payers for conventional DRAM and NAND; they are the other side of the price.

1. Late Nov 2026TrendForce normally publishes its 3Q26 DRAM and NAND revenue rankings.
2. Dec 2026Micron reports fiscal Q1 2027 against its guidance of $61.5 billion.
3. Jan-Feb 2027Quarterly results from SK hynix, Samsung, SanDisk, Kioxia and ASML for the fourth quarter.
4. Early 2027First samples of HBF-based inference devices expected, per a 2026 report.
5. 2027-2028SK hynix says long-term agreements already cover more than half of capacity.
6. 2028 and beyondMicron's cleanroom expansions aimed at late calendar 2028 and beyond.

• No primary dated source for HBM price per gigabyte, or for capital spending per bit.
• Samsung's memory-segment results and HBM revenue are not confirmed; the HBM revenue ranking among suppliers is contested (secondary estimate versus TrendForce commentary).
• The Entity List status of CXMT and YMTC reported for February 2026 could not be confirmed from the Federal Register.
• Current figures for the Korean companies' China fabs licensing, CHIPS grants and CXL adoption were not retrieved.
• Latest results for SanDisk, Kioxia, Western Digital, Seagate, Applied Materials, Lam, Tokyo Electron, Advantest and Hanmi were not retrieved; their rows describe roles, not current numbers.
• Several figures come from secondary summaries of TrendForce releases, and some secondary share tables did not reconcile; original reports should be checked.